We suspected the area may be sub-optimal as a result. We were able to meet our performance goals, but Our previous DCG-Innovus flow had significant path slack differences between Violation clean, and routing clean (low DRCs) with minimal standard cell Each of the blocks must meet the 2.5+ GHz target frequency, be hold Our clock network is a hybrid mesh with local cluster connection for minimal Sub-system "Marx_Bros" which broke into 5 physical blocks ranging fromįrom 80,000 instances to 1.5 M instances.
GENUS II DEFAULT LOGIN TIME CLOCK PLUS
This time our design was a 2.5+ Ghz 16nm custom high-performance CPU plus The rest of the flow remained the same - Cadence timing signoffīackend (Tempus, Quantus) and Mentor ATPG/scan test and Calibre physical Would happen if we swapped it in place of DC-Graphical inside our Innovus Since Genus Physical passed our "Godzilla" benchmark, we decided to see what Working on the right optimization problems.īENCHMARKING GENUS PHYSICAL VS. Genus FEPs were also in the Innovus top 100 FEPs. It also had a good prediction of pre-CTS Innovus placement optimization. Throughput and was within our 1.5-day runtime limit - with 4.5 hours to With a total of 24 cores, Genus-RTL Physical got a 4 hour per million cell Threaded and hits a speed improvement wall between 8 and 16 CPU cores.) (In contrast, DC-Graphical is only multi. This is not using a top-down time budgeting which oftenįalls into sub-optimal results. Into partitions, carving up cones of logic to minimize reconvergent pathsīetween partitions. Genus-RTL Physical is partition-based synthesis that does both distributedĪnd multi-threaded optimization. Than 2 days and we never saw it converge.
For example, our DC-Graphical runs were taking MUCH longer
You run into bad schedule hits if will you have trouble getting convergence Thumb is that if physical synthesis takes more than 2 days for any design, The challenge here was to get a good physical synthesis result in underġ.5 days in order to have a predictable PPA through to PnR. Of the blocks still needs to be 4M cells, which is pretty big. It's techinically possible to divide "Godzilla" into 3 blocks, but it wouldīe unnatural - with a lot of interconnect between the sub-partitions. We focused Genus Physical on a monster 7.8M cell block, 16nm, 750 MHz that Now the question became: "how does Genus-RTL Physical handle our blocks?" Put Innovus in the PnR socket in our flow.Ĭurious, since we were already in Innovus then, we decided to also try a So after out internal 16nm FinFET benchmark, we swapped out ICC/ICC2 and That worked,Īt 16nm FinFET came in we tried ICC/ICC2 and things begame to break in ourīenchmarks. Star-RC, IC Validator plus Mentor Calibre for golden sign-off. OUR FIRST LOOK AT CADENCE GENUS-RTL STANDALONEĪt 28nm we were an all-Synopsys house. Which is a tough question that has no good answer unless your RTL synthesis "Exactly what is the optimal routing topology for logic mapping It creates chicken-and-egg questions for our RTL synthesis tools. Even very short distance, low-fanout wires
Wires and high-fanout delays - to now also accounting for small stuff like This extra jump in wire delay hasĬhanged the classic physical synthesis problem from mostly predicting long To 7nm there is an ADDITIONAL order of magnitude difference (now 10,000X!)īetween wire delay and transistor delay. It the contact, routing, via, andĪt N16 a wire delay is 1,000X slower than a gate delay. ITRS predicting wire interconnect RC delay vs transistor gate delay from aĮditor's Note: BEOL is a fab term for "Back End of Line". Given to us in small managable incremental changes. The need for physical synthesis has been around since 90nm. It started because ofĭevice physics fundamentally changing as we move below 16nm. Not because of bad ICC2 or better Innovus software. This "tipping point" started happening at 16nm and is getting worse at 7nm What I wanted to point out is where you're half wrong in your RTL synthesis My group switched from ICC/ICC2 over to Innovus for 16nm PnR, but we keptĭC Graphical for our RTL synthesis. What you said here in your DAC'17 "Best of" report is half true and half Is now becoming a credible threat to Aart's Design Compiler monopoly. From the many user commentsīelow, it appears that Cadence Genus RTL, when paired with Innvous PnR, Happening in the RTL synthesis market, too. In PnR over the past few years - we might now be seeing a tipping point What makes this interesting is since Innovus has been eating ICC2's lunch Old Sci-Fi "The Butterfly Effect" story but for business. Now can have a large impact on future events. Subject: After 16nm benchmark, 7nm user swaps out DC-Graphical for Genus-RTLĪN RTL SYNTHESIS TIPPING POINT?: Roughly 17 years ago, a new businessīook came out, "The Tipping Point", that emphasized how little things
0 kommentar(er)
